Staff Packaging Engineer

About Us

Adeia Inc. (Nasdaq: ADEA) the technology company known for developing foundational innovations that enable next-generation solutions for the semiconductor and media industries, headquartered in San Jose, CA, with approximately 150 employees, primarily in North America. Adeia invents, develops, and licenses fundamental innovations that shape the way millions of people explore and experience entertainment in an increasingly connected world. From TVs to smartphones, and across all types of entertainment experiences, Adeia’s technologies allow users to manage content and connections in a way that is smart, immersive, and personal. Adeia is proud to be recognized by U.S. News & World Report as one of the “Best Companies to Work For" in 2025 - 2026.

Position Summary

The Staff Packaging Engineer develops and optimizes semiconductor packaging solutions from silicon die through PCB-level integration. This role supports advanced packaging development, structural and thermal analysis, assembly process integration, reliability, qualification, and manufacturing readiness for leading-edge semiconductor products. Working closely with R&D teams, component suppliers, CMs/OSATs and customers, the role supports package development and high-volume manufacturing readiness while driving continuous process improvement.

Key Responsibilities

Package Development

Develop and optimize semiconductor packaging solutions from die to PCB integration.
Support advanced packaging technologies including 2.5D and 3D integration.
Define package stack-ups, substrates, interconnects, materials, and PCB interface requirements.
Support engineering builds, qualification activities, and HVM readiness.
Collaborate with R&D teams, substrate/PCB suppliers, and CMs/OSATs
Structural and Thermal Analysis

Perform structural, thermomechanical, and thermal simulations using FEA tools.
Analyze package reliability risks including stress, deformation, fatigue, etc..
Optimize package designs for mechanical robustness, manufacturability, and thermal performance.
Correlate simulation results with lab data and failure analysis findings.
Assembly and Manufacturing Support

Develop and optimize assembly processes including flip-chip, die attach, underfill, molding, singulation, SMT, and PCB-level assembly.
Provide hands-on support for prototype builds, troubleshooting, and yield improvement.
Work with suppliers and CMs/OSATs to improve assembly processes and manufacturing readiness.
Support root cause analysis and corrective actions for assembly and reliability issues.
Reliability and Customer Support

Define and execute package qualification plans per JEDEC and relevant standards.
Support reliability testing and failure analysis activities.
Support technical discussions related to package integration, manufacturability, and HVM readiness.
Communicate technical findings and drive continuous process improvements.

Key Competencies

Semiconductor Package Development
Structural, Thermal & Reliability Analysis
Assembly Process Optimization & Manufacturing Readiness
Failure Analysis & Technical Problem Solving
Cross-Functional Collaboration
Technical Communication & Influence
Continuous Improvement & Process Optimization

Minimum Qualifications

Master’s degree in Mechanical Engineering, Electrical Engineering, Materials Science, Physics, or related field.
7+ years of post-graduate experience in semiconductor, packaging, assembly, engineering, or advanced packaging R&D; candidates with a PhD in a relevant field may be considered with fewer years of industry experience
Experience developing semiconductor packaging solutions from die through PCB assembly.
Experience with semiconductor assembly processes, manufacturing flows, and engineering builds.
Hands-on experience with assembly process troubleshooting, yield improvement, and manufacturing readiness.
Experience with structural and thermomechanical simulation tools such as ANSYS.

Preferred Qualifications

PhD in Mechanical Engineering, Electrical Engineering, Materials Science, Physics, or related engineering discipline.
Experience with advanced packaging technologies including TSV, fan-out, chiplets, heterogeneous integration, or hybrid bonding.
Experience working with CMs, OSATs, and high-volume manufacturing environments.
Familiarity with SI/PI fundamentals, package layout, and EDA tools.

Location: San Jose, CA

San Jose, CA Range: $170,000 - $205,000
Bonus Target: 10% of annualized base pay
Restricted Stock Units Target (as a % of annualized base pay): 45%
The base compensation is based on the primary work location, as ranges are location-specific. Actual compensation will depend on factors such as skills, experience, and qualifications.
Benefits include medical, dental, vision, 401(k), paid time off, and other company programs.

Life @ Adeia:

At Adeia, we are dedicated to creating a workplace where all employees have a voice and
sense of belonging, feel safe and valued, and are acknowledged for how their unique
differences contribute to organizational culture and business outcomes.
Our employees and their families are important to us, and our comprehensive pay, stock,
and benefits programs reflect that. Adeia supports personal well-being, builds financial
security, and enables employees to share in our collective success.

Rewards include:

Competitive compensation (salary, equity, and bonuses) and comprehensive benefits are designed to foster work-life balance, care for your health, protect your finances, and help you save and invest for the future.
Generous paid time away from work, including flexible time off, holidays and sick time, health and wellness initiatives, and a charitable match program to help you give back to your community.
Great benefits, which vary by location and can be site-specific: employee discounts, transportation reimbursements, and fitness facilities.
A flexible, hybrid work environment combining the best of in-office collaboration and community-building along with the benefits of working from home.