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EdgeQ Technologies is a leading US Staffing providers

VLSI Design Engineer

  • $95k – $165k • No equity
  • |
    Austin • 
    +1
  • |2 years of exp
  • |Full Time
Posted: today• Recruiter recently active
Job Location
Austin • 
San Jose • 
Remote Work Policy

In office - WFH flexibility

Visa Sponsorship

Not Available

RelocationAllowed
Skills
Verilog
VLSI Design
ASIC Design
RTL Design
Hiring contact
Manideep Gujjala
Founder
image

About the job

  • Job Title: VLSI Design Engineer
  • Locations: San Jose, California | Austin, Texas | Raleigh, North Carolina, United States
  • Work Mode: Full-Time | On-site / Hybrid
  • Experience: 2–8 Years
  • Salary Range: $95,000 – $165,000 per year
  • Employment Type: Full-Time

Job Summary

We are seeking a skilled and motivated VLSI Design Engineer to join our semiconductor engineering team in the United States. The ideal candidate will be responsible for designing, developing, verifying, and optimizing digital integrated circuits (ICs) and semiconductor components.

The candidate should have strong knowledge of RTL design, Verilog/SystemVerilog, ASIC design flows, and functional verification methodologies.

Key Responsibilities

  • Design and develop digital circuits and RTL modules for ASIC and SoC platforms.
  • Write, review, and optimize RTL code using Verilog and SystemVerilog.
  • Perform RTL design, simulation, synthesis, and functional verification.
  • Work on ASIC design and implementation flows.
  • Collaborate with physical design, verification, and semiconductor engineering teams.
  • Analyze timing, power, and area (PPA) requirements.
  • Debug design issues and resolve functional and performance-related problems.
  • Perform logic synthesis and support timing closure activities.
  • Review design specifications and prepare technical documentation.
  • Participate in design reviews and contribute to continuous design improvements.

Required Skills & Qualifications

  • 2–8 years of experience in VLSI Design or Semiconductor Engineering.
  • Strong knowledge of Verilog and SystemVerilog.
  • Experience with RTL design and digital logic design.
  • Understanding of ASIC and SoC design methodologies.
  • Knowledge of synthesis, simulation, and verification processes.
  • Familiarity with timing analysis and optimization.
  • Understanding of CMOS technology and semiconductor fundamentals.
  • Experience with EDA tools such as Synopsys, Cadence, or Siemens EDA.
  • Strong analytical, debugging, and problem-solving skills.

Preferred Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, or a related field.
  • Experience with FPGA prototyping and ASIC implementation.
  • Knowledge of UVM-based verification methodologies.
  • Familiarity with static timing analysis (STA).
  • Understanding of low-power design techniques.
  • Experience with scripting languages such as Python, Tcl, or Perl.
  • Knowledge of physical design, floorplanning, placement, and routing.

Salary & Benefits

  • Annual Salary: $95,000 – $165,000.
  • Competitive compensation based on skills and experience.
  • Health, dental, and vision insurance.
  • Paid time off and holidays.
  • Retirement savings benefits, where applicable.
  • Professional development and technical training.
  • Career advancement opportunities.

Job Locations

  1. San Jose, California, United States.
  2. Austin, Texas, United States.
  3. Raleigh, North Carolina, United States.

How to Apply

Interested candidates can submit their updated resume along with contact details and relevant VLSI Design Engineering experience.

Equal Opportunity Employer: We welcome qualified candidates from diverse professional backgrounds and encourage applications from eligible candidates across the United States.

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