ASIC Design Verification

Job Description: ASIC Design Verification Engineer

Experience: 5+ Years
Job Type: Full-Time / Contract
Location: USA
Company: Scaledge Technology Ltd.

Job Overview

Scaledge Technology Ltd. is seeking an experienced ASIC Design Verification Engineer with a minimum of 5 years of experience in ASIC and SoC Design Verification. The ideal candidate will have strong expertise in SystemVerilog, Universal Verification Methodology (UVM), testbench development, simulation, debugging, and functional verification of complex digital designs.

The candidate will be responsible for developing and executing comprehensive verification environments, validating RTL designs against functional specifications, identifying design issues, and ensuring quality and reliability before silicon tape-out.

The role requires hands-on experience in IP-level and SoC-level verification, protocol-based verification, coverage-driven verification, and collaboration with RTL designers and cross-functional engineering teams.

Key Responsibilities

Develop, maintain, and enhance reusable verification environments using SystemVerilog and UVM.

Develop and execute verification plans, test plans, testbenches, test scenarios, and directed and constrained-random test cases.

Perform functional verification of ASIC, SoC, IP, and subsystem-level designs.

Develop UVM components, including agents, drivers, monitors, sequencers, scoreboards, and reference models.

Verify standard protocols and interfaces such as AXI, AHB, APB, PCIe, DDR, USB, Ethernet, and other high-speed interfaces, depending on project requirements.

Perform constrained-random testing, assertion-based verification (SVA), and functional and code coverage analysis.

Run simulations using industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, and Siemens Questa.

Debug simulation failures, perform root cause analysis, and collaborate with RTL designers to resolve functional issues.

Develop and maintain verification scripts and automation using Python, Perl, Shell, or other scripting languages.

Analyze functional coverage, identify verification gaps, and implement strategies to achieve coverage closure.

Participate in design reviews, verification planning, regression reviews, and project status meetings.

Support IP integration, SoC integration, and pre-silicon verification activities.

Document verification results, debug findings, test coverage, and project progress.

Work closely with design, architecture, firmware, and validation teams to ensure successful verification milestones.

Required Qualifications and Technical Skills

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related technical discipline.

Minimum 5 years of hands-on experience in ASIC, SoC, or IP Design Verification.

Strong proficiency in SystemVerilog and UVM-based verification methodology.

Solid understanding of digital design concepts, RTL architecture, and hardware design fundamentals.

Experience developing and maintaining reusable UVM testbenches and verification components.

Hands-on experience with simulation, debugging, regression management, and functional coverage closure.

Strong knowledge of constrained-random verification, assertions, and coverage-driven verification methodologies.

Experience with EDA simulation and debugging tools such as Synopsys VCS, Cadence Xcelium, Questa, and Verdi.

Proficiency in scripting languages such as Python, Perl, or Shell for test automation and regression management.

Experience with bus protocols and interfaces such as AXI, AHB, APB, PCIe, DDR, or other relevant industry-standard protocols.

Strong analytical, problem-solving, communication, and debugging skills.

Preferred / Good-to-Have Skills

Experience in SoC-level and subsystem-level verification.

Knowledge of Formal Verification and assertion-based verification methodologies.

Experience with FPGA prototyping, emulation platforms, and hardware-assisted verification.

Exposure to firmware-driven verification and hardware-software co-verification.

Familiarity with low-power verification, clock-domain crossing (CDC), and reset-domain crossing (RDC).

Experience with protocols such as USB, Ethernet, MIPI, I2C, SPI, or SerDes.

Knowledge of Linux environments, Git, and continuous integration workflows.

Experience with post-silicon validation and silicon bring-up activities.

Education

Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

Master's degree in a relevant engineering discipline is preferred.

Desired Candidate Profile

Strong hands-on verification experience with a problem-solving mindset.

Ability to independently develop verification environments and debug complex design issues.

Good understanding of verification methodologies and hardware design principles.

Ability to work effectively with geographically distributed engineering teams.

Strong ownership of verification deliverables, schedules, and coverage closure.

About Scaledge Technology Ltd.

Scaledge Technology Ltd. is a semiconductor engineering services company providing ASIC, SoC, FPGA, Design Verification, Physical Design, DFT, Emulation, Post-Silicon Validation, and Embedded Software engineering solutions. Our engineering teams support global semiconductor customers in developing next-generation technologies and silicon products.