Physical Design Engineer

Experience: 5+ Years
Job Type: Full-Time / Contract
Location: USA
Company: Scaledge Technology Ltd.

Job Overview

Scaledge Technology Ltd. is seeking an experienced ASIC Physical Design Engineer with 5+ years of hands-on experience in RTL-to-GDSII implementation, physical design, and semiconductor backend design methodologies.

The ideal candidate will have strong expertise in physical design implementation, floorplanning, placement, clock tree synthesis (CTS), routing, timing optimization, and physical verification. The candidate will work closely with RTL design, synthesis, DFT, STA, and signoff teams to deliver high-performance, power-efficient, and area-optimized ASIC/SoC designs.

The role requires practical experience with industry-standard EDA tools, advanced technology nodes, timing closure, and physical design signoff methodologies.

Key Responsibilities

Perform end-to-end physical design implementation from synthesized netlists to GDSII.

Execute floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical design optimization.

Perform timing analysis and timing closure to meet design performance requirements.

Optimize designs for Power, Performance, and Area (PPA).

Conduct pre-placement and post-placement optimization to address setup and hold timing violations.

Perform clock tree synthesis, clock skew optimization, and clock latency management.

Analyze and resolve signal integrity, congestion, transition, capacitance, and fanout violations.

Perform static timing analysis (STA), including setup and hold analysis across multiple operating modes and process-voltage-temperature (PVT) corners.

Work on timing constraints development and validation using Synopsys Design Constraints (SDC).

Perform power integrity analysis, including IR drop and electromigration (EM) analysis.

Resolve design rule check (DRC), layout versus schematic (LVS), and other physical verification violations.

Collaborate with RTL, synthesis, DFT, and design teams to resolve implementation challenges.

Develop and maintain automation scripts using Tcl, Python, Perl, or Shell.

Support engineering reviews, implementation methodology improvements, and signoff activities.

Prepare physical design reports, timing reports, congestion reports, and implementation documentation.

Support final GDSII generation and tape-out readiness.

Required Qualifications and Technical Skills

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related technical discipline.

Minimum 5 years of hands-on experience in ASIC Physical Design.

Strong understanding of the complete RTL-to-GDSII physical design flow.

Hands-on experience with floorplanning, power planning, placement, CTS, routing, and timing optimization.

Strong knowledge of Static Timing Analysis (STA), timing constraints, setup and hold analysis, and timing closure.

Experience with Synopsys Design Constraints (SDC), multi-mode multi-corner (MMMC) analysis, and PVT corners.

Experience with power optimization, congestion analysis, signal integrity, and physical design debugging.

Knowledge of physical verification methodologies, including DRC, LVS, and antenna checks.

Experience with scripting and automation using Tcl, Python, Perl, or Shell.

Strong understanding of digital logic, CMOS fundamentals, semiconductor technologies, and ASIC implementation methodologies.

Experience working with cross-functional design, verification, synthesis, and signoff teams.

EDA Tools and Technologies

Hands-on experience with one or more of the following industry-standard tools:

Physical Design Tools:

Synopsys IC Compiler II (ICC2)

Synopsys Fusion Compiler

Cadence Innovus

Static Timing Analysis:

Synopsys PrimeTime

Cadence Tempus

Physical Verification and Signoff:

Synopsys IC Validator

Cadence Pegasus

Siemens Calibre

Synthesis and Supporting Tools:

Synopsys Design Compiler

Cadence Genus

Synopsys StarRC

Cadence Quantus

Preferred / Good-to-Have Skills

Experience working on advanced semiconductor technology nodes such as 7nm, 5nm, 4nm, 3nm, or other FinFET technologies.

Experience with hierarchical and block-level physical design implementation.

Knowledge of low-power design techniques, including multi-voltage domains, power gating, and UPF.

Experience with advanced clocking methodologies and multi-clock domain designs.

Knowledge of signal integrity, crosstalk analysis, and noise optimization.

Experience with ECO implementation and engineering change order flows.

Familiarity with DFT integration, scan chain considerations, and physical design impact of test structures.

Experience with high-speed interfaces, memory subsystems, and complex SoC designs.

Knowledge of Linux environments, Git, and design implementation automation.

Education

Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.

Master's degree in a relevant engineering discipline is preferred.

Desired Candidate Profile

Strong hands-on experience in ASIC Physical Design and backend implementation.

Ability to independently handle physical design blocks and drive timing closure.

Strong analytical and problem-solving skills.

Experience debugging complex physical design and timing issues.

Ability to work with cross-functional and geographically distributed engineering teams.

Strong ownership of project deliverables, implementation quality, and tape-out schedules.

About Scaledge Technology Ltd.

Scaledge Technology Ltd. is a semiconductor engineering services company providing ASIC, SoC, FPGA, Design Verification, Physical Design, DFT, Emulation, Post-Silicon Validation, and Embedded Software engineering solutions. Our engineering teams support global semiconductor customers in developing next-generation technologies and silicon products.