Jobs at QLogic - Page 4

• 5+ years in direct people management and technical leadership
• Deep expertise in high-speed SerDes architecture, analog/mixed-signal circuits, and data communication systems (NRZ and PAM4 at 56G, 112G, 224G+)

• Serve as a Techno functional SME for Oracle EBS modules (Procurement (Iproc, PO, RCV) and Finance (GL, AP, AR, FA).
• Drive solution design, architecture, and implementation of enterprise systems

• Leading architecture for data center SuperPod AI Infrastructure to meet customer requirement.
• Designing state-of-the-art system architecture for CXL & PCIE & UALink scale up fabric

• Architect and develop FPGA logic.
• Integrate common code blocks into designs.

• Participate in the design and implementation the PHY validation framework, which focues on automation, scalability, and modularity to support diverse hardware validation requirements.
• Collaborate with cross-functional teams (hardware, firmware, validation, and test engineering) to define validation goals, interface requirements, and automation strategies.

• Lead integration of an embedded RISC-V core (e.g., SiFive E24 Core) into chip validation environments
• Define MCU subsystem architecture: memory map, boot flow, and execution environment

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

• Participate in the design and implementation the PHY validation framework, which focues on automation, scalability, and modularity to support diverse hardware validation requirements.
• Collaborate with cross-functional teams (hardware, firmware, validation, and test engineering) to define validation goals, interface requirements, and automation strategies.

• Design network topology discovery and visualization for rack‑ and data‑center‑scale environments
• Architect telemetry collection from switches, NICs, and optical modules

• ​Develop run sets for nanotechnology and support Calibre, ICV and provide user support for DRC and LVS debugging to streamline physical verification flow. Automate and support physical verification flow for internal design tools group. Support tape-out and design-related foundry interface activities, physical verification CAD flow, and CAD flows for SOC integration. Develop and maintain validation procedures for physical verification flow and prepare user guides and documents. Job duties include some usage of full custom layout tools to review results and create validation test cases.

• Improve the design methodology and flow.
• Synthesis, timing closure and DFT support for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.

• Drive emulation bring‑up activities, including clock/reset sequencing, firmware boot, and system validation using pre‑silicon hardware models.
• Collaborate closely with Senior Emulation Engineers, RTL design, verification, and firmware teams to develop accurate hardware models, and ensure seamless integration into the emulation environment.

• In this role, you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development.
• Writing a verification test plan using random techniques and coverage analysis and working with...

• Bachelor’s degree in Information Systems, Computer Science, or related discipline
• 10+ years of experience in FP&A systems, enterprise applications, business analysis, or solution architecture

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

• Own the packaging technology roadmap for AI XPU, XPU-attach and Switch
• Define system-level package architecture including chiplet topology, interposer/substrate scaling, power delivery network strategy, and thermal design envelope.

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

• Design and develop firmware for the Marvell's diverse portfolio of Compute, Storage and Custom ASIC solutions.
• Partner closely with the hardware engineering team to bring up, test and validate the hardware reference platforms for our Compute, Storage, and Custom ASIC product lines.

• Create, document, and execute sub-system and top level test plans to verify design functionality.
• Build simulation environments (UVM/SystemVerilog/Python) to verify RTL/firmware designs and develop automated scripts for testing.