Jobs at MediaTek

MediaTek Genio edge AI processors power smart retail kiosks, robots, industrial vision systems and smart building devices. As our Field Application Engineer for the Northeast US and Eastern Canada, you will be the hands-on Linux expert our IoT customers rely on, from first evaluation board to mas...

• At least 6 months of hands-on experience with DFT methodologies, including scan insertion, scan compression, ATPG pattern generation, and at-speed testing.
• Ability to debug DFT patterns using gate-level simulations (GLS).

• Define, develop, and own GPU shader subsystem microarchitecture specifications.
• Lead RTL design for shader-related blocks, including shader pipelines, instruction issue, operand collection, register files, dependency tracking, and pipeline control.

• Analyze ADAS/Centralized car computer market for future SoC product trend and opportunities, especially in cabin-drive integration and AI-driven automotive applications.
• Conduct ADAS/CCC competition analysis and define product position/key features to capture the market.

• Bring up new platform boards and verify the major functions independently
• Regular software release and multiple branch conflict resolving

• Perform high-level architecture exploration and feasibility studies for next-gen electrical/optical interconnects (e.g., CPO, SerDes, arrayed optics)
• Conduct rapid link budget, SNR, BER, and channel margin evaluations using MATLAB and Python.

• Bring up new platform boards and verify the major functions independently
• Regular software release and multiple branch conflict resolving

• Preferred Qualifications
• - Master’s degree in Electrical Engineering, Computer Science, or a related field

• 8–12 years of B2B technology marketing experience, with a minimum of 3–5 years focused on AI/ML, generative AI, automotive or platform marketing, cloud infrastructure, or semiconductor marketing.
• Demonstrated fluency in AI compute — NPU and accelerator architecture, GPU compute for AI, and the trade-offs between training and inference, cloud and edge, throughput and power — with enough software stack knowledge (models, frameworks, runtimes, quantization, deployment) to connect silicon capability to real workloads.

• Key Development Technologies: System development with high-speed physical layer data transmission software development, hardware performance optimization, and product quality control.
• Main Objectives: Complete system integration for customized ICs in Enterprise/AI/xPU and related industries, and assist customers in mass production, especially SLT.

• Architect, develop, debug, and release embedded firmware for optical engine platforms.
• Define MCU/processor, memory, boot, and peripheral requirements for optical module and optical engine control subsystems.

• Lead and mentor a team of analog, mixed-signal, and power delivery engineers, providing technical direction and fostering a culture of innovation, execution excellence, and continuous learning.
• Define and drive the architecture, modeling, design, and validation of integrated voltage regulator (IVR) solutions for next-generation CPU, GPU, AI, and accelerator products.

• Key Development Technologies: System development with high-speed physical layer data transmission software development, hardware performance optimization, and product quality control.
• Main Objectives: Complete system integration for customized ICs in Enterprise/AI/xPU and related industries, and assist customers in mass production, especially SLT.

• Work with the engineering team to integrate MediaTek SOC platforms with customer
• Software development and integration for customizing software for customer product

• Platform Architecture Definition: Define the compute system architecture (workstation, 1U/2U, multi-node, OCP form factors) surrounding our Datacenter compute SoC.
• Power & Thermal Management: Architect system-level power delivery networks (PDN/VRM specs) and collaborate on advanced thermal solutions (air and liquid cooling) to meet strict datacenter TDP constraints.

• Platform Architecture Definition: Define the compute system architecture (workstation, 1U/2U, multi-node, OCP form factors) surrounding our Datacenter compute SoC.
• Power & Thermal Management: Architect system-level power delivery networks (PDN/VRM specs) and collaborate on advanced thermal solutions (air and liquid cooling) to meet strict datacenter TDP constraints.

• Education:
• - Bachelor's degree in Electrical Engineering, Electronics, or related field

• - Bachelor degree with 6 years of experience or equivalent.
• - Work closely with designers to discuss circuit concerns, and develop effective solutions together.

• Develop advanced algorithms for 6G modems - Implement high-level modem algorithms in C/C++ simulation platforms and perform design trade-off and optimization in terms of performance, complexity and power consumption - Collaborate with ASIC, DSP, and L1 design teams from different sites worldwide and provide a full support for fixed-point design, pre- and post-silicon verifications in the product development - Conducting future advanced research and development activities in wireless communication areas.

• Drive workload analysis programs (e.g., for Agentic AI) to support silicon product planning, articulating their impact and implications for system architecture from a market and competitive perspective. This involves understanding how future roadmap features or system capabilities, particularly those enabled by next-gen hardware (e.g., advanced power management, on-device LLMs running on xPU, new I/O features), can be leveraged for market advantage.