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DiscoverStartupsCelero CommunicationsJobs at Celero Communications: Explore current Opportunities
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Celero Communications
Actively Hiring
Optical connectivity for AI infrastructure51-200 Employees
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Jobs at Celero Communications

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Principal Physical Design Engineer

NewPosted 3 days ago

Principal Physical Design Engineer

  • RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
  • Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
In office • San Jose
$150k – $250k
Other Engineering

Principal High-Speed Analog Layout Design Engineer

NewPosted 2 weeks ago

Principal High-Speed Analog Layout Design Engineer

  • Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
  • Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
In office • Irvine
$150k – $250k
Other Engineering

ASIC Design Engineer – DSP / Analog / SerDes

NewPosted 1 month ago

ASIC Design Engineer – DSP / Analog / SerDes

  • Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
  • Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.
In office • Ottawa
Other Engineering

Principal Analog Design Engineer

NewPosted 1 month ago

Principal Analog Design Engineer

  • High speed analog circuit design, such as high-speed broadband amplifiers (VGA, CTLE, DRV, etc.)
  • Clock generation and distribution (VCOs, PLL, clock distribution, etc.)
In office • Vancouver
Other Engineering

Principal Physical Verification Engineer

NewPosted 1 month ago

Principal Physical Verification Engineer

  • Lead full chip Physical Verification effort
  • Own execution plans, schedules for full-chip
In office • San Jose
$150k – $250k
Other Engineering

Senior/Principal Full-Chip Physical Verification Engineer

NewPosted 2 months ago

Senior/Principal Full-Chip Physical Verification Engineer

  • Lead full chip Physical Verification effort
  • Own execution plans, schedules for full-chip
In office • San Jose
$150k – $250k
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