RTL Design & Verification Intern

Hardware Engineering Intern (ASIC/FPGA Verification & RTL)

Location: Remote

Duration: 3 to 6 Months

Commitment: Part-time

About the Role

We are looking for a hands-on, detail-oriented Hardware Engineering Intern to join our silicon design and verification team. In this role, you will help ensure that our digital designs work flawlessly before they ever touch physical silicon or an FPGA board.

You do not need to be an expert in complex verification methodologies like UVM to succeed here. Instead, we are looking for students and junior engineers with a solid foundation in digital logic who are comfortable writing RTL (Verilog or SystemVerilog). You will work alongside experienced hardware architects to write test benches, run simulations, and debug logic at the waveform level, gaining real-world experience in how modern chips are tested and verified.

What You Will Be Doing

• Write & Review RTL: Read, understand, and occasionally write synthesizable RTL code (Verilog/SystemVerilog) to help build or test digital blocks.
• Build Test Environments: Develop self-checking test benches to verify the functionality of FPGA and ASIC IP blocks.
• Simulate & Debug: Run simulations, analyse waveform outputs (using tools like GTKWave), and track down logic bugs to find out why a design failed.
• Automate the Process: Write Python or Bash scripts to automate simulation runs, parse log files, and report on test coverage.
• Collaborate & Learn: Work closely with design engineers to understand the microarchitecture and figure out the best ways to break (and fix) the design.

What We Are Looking For

• Digital Logic Fundamentals: A strong understanding of digital electronics, Boolean algebra, state machines, and clocking basics.
• RTL Coding Skills: Hands-on academic or personal project experience writing RTL using Verilog or SystemVerilog. You should be able to write basic combinational and sequential logic blocks from scratch.
• Familiarity with Simulation: Basic exposure to running RTL simulations using standard EDA simulators (such as ModelSim, Vivado, Icarus Verilog, or Verilator).
• Scripting Ability: Comfort using Python (or similar scripting languages) to automate tasks, move files around, or parse text logs.
• Hardware Debugging Mindset: A detective's approach to problem-solving. You enjoy looking at a failing waveform and tracing signals backward to find the root cause.

Bonus Points (Nice-to-Haves)

• Experience with Python-based hardware verification frameworks like Cocotb.
• Familiarity with open-source EDA tools (such as Verilator, Yosys, or Icarus Verilog).
• Hands-on experience flashing and debugging code on physical FPGA development boards (like Digilent, Xilinx, or Altera boards).
• A basic conceptual understanding of advanced verification concepts (Code Coverage, Assertions, or UVM).
• A GitHub repository showcasing a digital design project (e.g., a simple CPU, a memory controller, or a custom UART).

What We Offer

• Direct Mentorship: Work closely with senior hardware engineers who will teach you industry-standard debugging and verification techniques.
• Real-World Silicon Experience: Move beyond textbook problems and work on verification tasks that impact actual tape-outs and hardware deployments.
• Modern Tools & Frameworks: Learn how high-output engineering teams combine traditional hardware description languages with modern, software-driven testing approaches (like Python and C++ based simulators).
• Flexible Growth: Opportunity to lean more heavily into hardware design (RTL coding) or advanced verification architecture based on your interests.