Staff Analogue Designer, CMOS Modelling

Location: This role is based at our Oxford, England (UK) office, with the option to work a few days a week remotely.

Travel: Up to 5%

Job ID: 1765

Role:

We are looking for a Analogue Designer, CMOS Modelling to join our Cryo-CMOS IC team at IonQ based in our Oxford office. In this role, you will be responsible for owning full-chip mixed-signal CMOS modelling as a first-class part of our Cryo-CMOS development flow. This includes building the behavioural model of the chip that the whole team will simulate against, allowing the team to design, verify and validate the integrated circuits that control our quantum processors - the novel technology that sits at the very heart of our world-leading quantum computers. You will enable the team to work in conditions from room temperature down to a few kelvin. This work will allow the team to meet our research and development goals, contributing directly to our ability to deliver on our technological milestones.

In this role you’ll play an important part in shaping the modelling methodology, standards and sign-off criteria that support our work in building the world’s most advanced quantum systems.

Responsibilities:

In this position, you will work on deriving behavioural models from first-principles mathematics to support the delivery of cryo-CMOS ASICS for our trapped-ion quantum processors. You will implement these models in Verliog-A, Verliog-AMS and real-number models, and correlate these against schematic and measured silicon. You will have the opportunity to set modelling standards across the whole team, raising the bar of quality so models can be used to inform and drive tapeout decisions. In turn this will raise the modelling capability of the engineers around you, contributing directly to the success of IonQ's quantum computing roadmap.

Key responsibilities include:

• Own the full-chip modelling strategy, including model architecture, abstraction levels, accuracy targets and sign-off criteria, and implementing across the whole IC development flow
• Develop Verilog-A and Verilog-AMS models of analogue blocks (references, DACs, switches, regulators, clock distribution) and assemble them into a simulatable full chip
• Build real-number models (SystemVerilog nettype/UDN, legacy wreal) so the full chip runs in digital verification and regression at speed
• Derive models from mathematics, for example turn a transfer function, a Z-parameter network description or a MATLAB analysis into robust, convergent Verilog-A with well-behaved tolerances
• Define and run model-versus-schematic correlation, to keep models in sync with design releases, and feed measured silicon behaviour, back into the flow
• Stand up mixed-signal co-simulation and regression (Cadence AMS Designer, Xcelium with Spectre); contribute to block-level design reviews and mentor engineers on modelling craft

Requirements:

To be successful, you will need 10+ years of deep analogue and mixed-signal design and modelling experience. Ideally this include working with models used in production tapeout flows. You will also have experience with expert Verilog-A and Verilog-AMS and strong real-number modelling. We’re looking for someone who can derive a model from equations and implement these end to end. You should also be able to judge what to model and at what fidelity, and align with the wider team on what a model does and does not promise.

You’d be a great fit with:

• Strong mathematical foundations, including experience with linear systems, Laplace and z-domain analysis, network (Z-) parameters, noise and non-linearity
• Fluency in a production Cadence flow, such as working with simulation environments like Virtuoso, Spectre, Xcelium and AMS Designer or similar
• Experience working with SystemVerilog, MATLAB or Python/NumPy for analysis and model validation
• Extreme-environment silicon experience such as, cryogenics and space

You should be able to work along designers, verification and system engineers and contribute effectively within a fast moving, highly technical team.