Verification Engineer

The ideal candidate will bring over 6+ years of industry experience, demonstrating a strong track record in verifying complex design blocks at the IP, Sub-system, or SoC level using SystemVerilog/UVM and related technologies. A deep understanding of PCIe protocol and its verification is essential. They should feel confident creating and executing test plans alongside design and verification teams in a metric-driven environment.

Key responsibilities include developing and enhancing SystemVerilog/UVM-based testbenches to verify new features across client, server, graphics, and semi-custom interconnects—including PCIe-based subsystems. The candidate should thoroughly understand testbench architecture, build expertise in verification components, and contribute to reusable infrastructure. Driving verification closure using coverage and quality metrics is crucial. Additionally, mentoring and leading junior engineers, guiding them on best verification practices, is expected.

Preferred experience involves strong proficiency in IP or Sub-system level ASIC verification and hands-on experience with PCIe protocol (Gen3/Gen4/Gen5 preferred) and its verification. Candidates should also have experience architecting and developing complex verification environments and infrastructure, including scripting in Perl, Ruby, Make, or similar languages. Exposure to RTL design, software development, formal verification, or related areas is valued, along with extensive experience in UVM testbench development for complex designs. A minimum of 10 years of relevant industry experience is preferred.