- B2C
- Early StageStartup in initial stages
- Top InvestorsThis company has received a significant amount of investment from top investors
In office - WFH flexibility
Not Available
About the job
About Ixana
Ixana is a Purdue University spinoff pioneering brain-inspired wearable computing. We've developed Wi-R, a patented communication tech that's 100x more energy-efficient than Bluetooth or Wi-Fi. Join our 60-person team building the next era of real-time, AI-powered human-computer interaction.
We provide comprehensive relocation support for candidates based outside Bengaluru.
The Wi-R Revolution
Wi-R is our patented non-radiative near-field communication technology that creates secure "wire-like wireless" experiences through small E-field bubbles around your body. This breakthrough enables unprecedented energy efficiency at sub-0.1 nanojoules per bit, making long-term wearable and implantable devices finally practical.
See Wi-R in Action: High-speed data, transferred through skin contact - Demonstration of Wi-R communication
What You’ll Do
- Perform RTL integration of internal/external IPs and subsystems into top-level SoCs.
- Develop and maintain RTL wrappers, interconnect logic, and clock/reset infrastructures.
- Run lint, CDC, and early synthesis checks to ensure high-quality integration.
- Collaborate closely with design, verification, and physical design teams to ensure clean handoff.
- Debug simulation and synthesis issues at both block and chip levels.
- Maintain and automate integration flows using Python/Perl/Tcl.
- Contribute to design reviews and document integration flows.
What We're Looking For
Required:
- 2-6 years of experience in RTL design and SoC/IP integration.
- Strong RTL skills using Verilog/SystemVerilog.
- Experience with AXI/AHB/APB protocols and interconnect architectures.
- Hands-on experience with tools like Synopsys Design Compiler, Spyglass, or similar.
- Proficiency in scripting languages Python, Perl, Tcl for flow automation.
- Understanding of synthesis, timing, and SoC assembly flows.
Preferred:
- Exposure to UPF/CPF and low-power design methodologies.
- Experience with SoC integration frameworks and custom EDA automation.
- Familiarity with high-performance, low-power compute architectures.
Compensation & Benefits
- Competitive base salary aligned with experience
- Cash bonus + meaningful early-stage equity
- Relocation support, partner job-search assistance
- Health insurance, paid leave, performance incentives, and employee rewards
- Inventor awards for patents and contributions
Why Join Us
- Work on cutting-edge deep tech that shapes the future of human-computer interaction
- Collaborate with world-class SoC, RF, mixed-signal, and wearable computing engineers
- Full ownership from architecture to silicon
- Fast-paced, transparent, and deeply technical culture
- Global exposure and opportunities to grow into lead roles
About the company
- B2C
- Early StageStartup in initial stages
- Top InvestorsThis company has received a significant amount of investment from top investors
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