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Celero Communications
Actively Hiring
Optical connectivity for AI infrastructure

SerDes Lead Designer

  • $150k – $250k
  • |
  • |10 years of exp
  • |Full Time
Posted: 2 months ago
Job Location
Remote Work Policy

In office - WFH flexibility

Visa Sponsorship

Not Available

RelocationAllowed
Skills
Matlab
SystemVerilog
Signal Integrity
Verilog-A
Power Integrity
Phase Interpolators
tDCS
Physical Layout
DLLs
Analog/mixed-Signal Circuits
High-Speed PLLs
Digitally Assisted Analog Circuits
Background Calibration
Adaptive Loops
SerDes IPs

About the job

About The Job

We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI.

Preferred Location -On-Site at our Irvine, CA HQ

Alternate Location - San Jose, California; Vancouver, British Columbia; Ottawa, Ontario

Candidate will have the opportunity to architect and design SerDes for next generation transceivers.

What You Will Do

  • Define architecture, specifications, and circuit topologies for next-generation SerDes
  • Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgeting
  • Design high-performance analog/mixed-signal circuits in advanced node technologies
  • Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
  • Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area
  • Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
  • Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets
  • Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
  • Correlate silicon measurements with simulated data, and lead performance optimization in the system environment

What You Will Bring

  • Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
  • Proven record of taking high-speed SerDes design to tape-out and volume production
  • Experience in lab bring-up, characterization, and debugging designs that reach out production
  • Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
  • Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
  • Strong communication and documentation skills

Salary Range

$150,000 - $250,000 Annually

The final offer will be determined based on job-related skills, experience, qualifications, and location.

About the company

Celero Communications company logo

Celero Communications

Actively Hiring
Optical connectivity for AI infrastructure51-200 Employees
Company Location
Laguna Beach
Company Size
51-200
Learn more about Celero Communications image

Funding

AMOUNT RAISED
$99M
FUNDED OVER
1 round
Round
B
$99999994
Series B - Nov 2025

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