IC Verification and Test Engineer

We are developing a novel optical interconnect for interfacing with the brain and seeking an IC Verification and Test Engineer to work in the development, verification, and testing of analog and mixed-signal ASICs.

Role Responsibilities

• Develop detailed simulation, verification, and test plans for analog and mixed-signal circuit simulators, and automate this flow using scripting languages
• Perform detailed simulations for analog, digital, and mixed signal CMOS ICs and ASICs, to verify circuit operation and compliance against target specifications before fabrication
• Perform wafer probing tests to determine the manufacturing yield and spread of performance parameters
• Perform detailed tests according to the test plans to check the functionality of the packaged parts, and measure performance parameters to see if they meet the target specifications
• Develop all the test Firmware and Software to be used for the verification and testing of the chips
• Prepare detailed documentations for the verification and test results of the IPs and chips, and prepare technical datasheets for the products tested
• Define specifications for all the test hardware and boards to be used for verification and testing

Key qualifications:

• 2+ years experience in the verification and testing of analog and mixed-signal IPs and ASICs using commercially available analog and mixed-signal circuit simulators
• Experience in the design and modeling of analog building blocks, such as bandgap voltage references, voltage and current mode DACs, and ADCs, low-noise amplifiers (LNAs), PLLS, DLLs, differential I/O circuits using Verilog-A and SystemVerilog
• Experience in Real-Number-Modeling (RNM) in SystemVerilog
• Experience in full-chip transistor level simulation using fast-Spice simulators used in the industry
• Familiarity with CMOS, LVDS, CML type IO devices, and simulating and modeling them at Spice and IBIS level
• Experience in development of verification and test plans for analog and mixed-signal ASICs
• Experience in chip-bring-up procedures at die and wafer level using manual or automated probe station and standard laboratory test equipment
• MSc in Electrical Engineering

Preferred qualifications:

• Familiarity with FPGA programming for chip testing and IP verification / emulation
• Good command on scripting languages (e.g. Python) to automate design and test procedures, and analyze / visualize verification and test results
• Familiarity with Printed Circuit Board (PCB) design at schematic and layout level, using commercial and open-source tools such Altium or KiCad

Salary/Pay Range:

For individuals hired to work in California, Science is required by law to include a reasonable estimate of the compensation range for this role. We determine your level based on your interview performance and make an offer based on geo-located salary bands. The base salary range for this full-time position is $140,000 – $200,000 + equity + benefits. Within the range, individual pay is determined by several factors, including job-related skills, experience, and relevant education or training. Please keep in mind that the equity portion of the offer is not included in these numbers.

Benefits:

At Science, our benefits are in place to support the whole you:

• Competitive salary and equity
• Medical, dental, vision and life insurance
• Flexible vacation and company-paid holidays
• Healthy meals and snacks provided onsite
• Paid parental, jury duty, bereavement, family care and medical leave
• Dependent Care Flexible Spending Account, subsidized by Science
• Flexible Spending Account
• 401(k)