Principal R&D Process Engineer

Diamond Foundry Inc. is solving the thermal limitation at the foundation of today's most exciting tech industries -- AI & cloud compute, electric-car power electronics, and 5G/6G wireless. We have managed to produce the world's first single-crystal diamond wafers and are now on a mission to put a diamond behind every chip. We are the rare unicorn that has grown fast and profitably. We received $515m in funding and are executing a multi-$B expansion plan for one of the greenest forms of tech manufacturing: converting greenhouse gas into diamond wafers using zero-emission energy.

We're seeking a highly skilled and experienced R&D Process Engineer to pioneer the development of processes enabling the application of diamonds in AI chips and power electronics. As an integral part of our seasoned team of mechanical, electrical, and materials engineers, you will play a key role in advancing the development of the Si thinning and polishing process to enable advanced bonding for maximizing diamond-enhanced performance. An ideal candidate brings expertise in Si thinning/polishing processes and a track record of on-time, within-budget project delivery through effective cross-functional teamwork.

Responsibilities:

• Develop 200mm/300mm CMOS wafer thinning/polishing processes to achieve ultrathin Si with semiconductor grade flatness and roughness.
• Develop temporary bonding processes for device wafer/die on carrier wafers to support subsequent thinning and/or permanent bonding processes.
• Develop technology and processes to singulate thinned device wafers bonded on carrier wafers.
• Engage with equipment vendors to facilitate tool acquisition, installation, and qualification.
• Design and execute DOE to optimize the process to achieve high quality, low cost, and good manufacturability, and create comprehensive documentations of process control scheme for the operation team to ensure smooth production ramp.

Requirements:

• Minimum of 5 years of experience in the thinning/polishing process and equipment in the semiconductor, HDD, MEMS, or related industries, and experience in temporary bonding adhesive and process is a plus.
• Solid understanding of surface and substrate roughness, cleanness, flatness, warpage characterization metrologies, including AFM, WLI, profiler, CSAM, CLSM.
• Skilled in statistical data analytics, including DOE, JMP, SPC, APC and FMEA, and experienced in Lean Manufacturing/Six Sigma methodologies and practices.
• Effective communication skills and ability to thrive in a cross-functional development team.
• Position requires the successful candidate to be onsite at Fremont and San Jose facilities.