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Voltai
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Developing super-intelligence to accelerate the pace of hardware innovation1-10 Employees
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Other Engineering

Synthesis & Static Timing Analysis (STA) Engineer

NewPosted 1 week ago

Synthesis & Static Timing Analysis (STA) Engineer

  • Own logic synthesis and constraint development (SDC) for blocks and full chips.
  • Drive timing closure across corners and modes, working with RTL and physical design teams.
In office • Palo Alto
Other Engineering

CAD & Flow Methodology Engineer

NewPosted 1 week ago

CAD & Flow Methodology Engineer

  • Build and maintain design flows spanning RTL, synthesis, STA, place and route, and signoff.
  • Integrate commercial EDA tools with Voltai's AI agents and data pipelines.
In office • Palo Alto
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