Jobs at Delos Data

• · Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field · 5+ years of experience in RTL design · Strong hands-on experience with Verilog/SystemVerilog · Solid understanding of synchronous digital design and microarchitecture principles · Experience with simulation and debug tools (e.g., VCS, Questa, Verdi, DVE) · Familiarity with synthesis, timing, and physical design constraints · Strong analytical and problem-solving skills · Clear written and verbal communication skills for cross-functional collaboration · High attention to detail and ability to deliver high-quality design outcomes · Ability to work independently and manage tasks to completion, including AI-assisted workflows

Who we are:
We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.

• Collaborate across the stack to influence the design of our foundational technology, ensuring it meets the needs of next-generation AI models.
• Identify and resolve performance bottlenecks in distributed training and inference workloads through deep-dive analysis of the software-hardware interface.

• Design, develop, and maintain a robust automated testing framework from the ground up that supports distributed AI training and inference workloads.
• Develop complex test plans that go beyond unit tests, focusing on end-to-end system integration, stress testing, and hardware-software boundary conditions.

• Serve as the dedicated technical owner for a strategic customer's production deployment of our software.
• Work hands-on in the customer's AI data center environment, including GPU/XPU clusters, high-speed fabrics, schedulers, and orchestration layers.

• Collaborate across the stack to influence the design of our foundational technology, ensuring it meets the needs of next-generation AI models.
• Identify and resolve performance bottlenecks in distributed training and inference workloads through deep-dive analysis of the software-hardware interface.

• Design, develop, and maintain a robust automated testing framework from the ground up that supports distributed AI training and inference workloads.
• Develop complex test plans that go beyond unit tests, focusing on end-to-end system integration, stress testing, and hardware-software boundary conditions.

• Drive implementation and register-level configuration of high-speed SerDes IP blocks across custom hardware systems.
• Own transceiver equalization tuning, including CTLE, FFE, and DFE tap optimization, to maximize eye margin and minimize bit error rates across cable, backplane, and board-level topologies.

• Select and design optimal multi‑die package types (MCM, 2.5D, 3D, fan‑out, CoWoS, InFO, CPC, CPO) balancing electrical performance, thermal behavior, cost, and manufacturability.
• Define package specifications, bump map and ball map, interposer requirements, and mechanical constraints.

• Own physical implementation of complex blocks and subsystems from synthesized netlist through signoff.
• Develop floorplans considering hierarchy, macros, interfaces, congestion, timing, power, and routability.

• Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies
• Create and execute coverage-driven verification plans aligned with design specifications