Analog layout engineer

High-Speed Analog Layout Engineer designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).

Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design
Parasitic & Noise Control: Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields). [1, 2, 3]
Reliability & Verification: Ensure complete closure on DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC, antenna rules, EM/IR (Electromigration / Infrared drop) reliability, and ESD protection
Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes (such as TSMC N3, N5, N7)
Experience at Lower node (N3, N5) is critical for this position.