Co-Founder & CTO (FPGA / Post-Quantum Cryptography)

You are Co-Founder & CTO of New Gen Cyber Solutions. You own the full
technical architecture:

• Lead RTL design of ML-KEM and ML-DSA acceleration cores in VHDL/Verilog
• on Xilinx UltraScale+ fabric (NTT optimization, Keccak integration)
• Architect the crypto-agile control plane on the P4S SOFTLESS platform
• Drive FIPS 140-3 (US) and ANSSI CSPN (EU) certification: security
• policy, algorithm documentation, test vector validation
• Lead DARPA SBIR and EIC Accelerator grant applications
• Collaborate directly with the P4S France engineering team in Paris
• Build and lead the engineering team post-Seed (SF Bay Area + remote)

─── WHO WE ARE LOOKING FOR ───

REQUIRED:

• PhD or equivalent in EE, CS, or Applied Mathematics
• (cryptographic engineering / hardware security)
• Expert RTL design: VHDL or Verilog, synthesis-ready, timing closure
• on Xilinx or Intel/Altera FPGA fabrics
• Deep implementation knowledge of ML-KEM and ML-DSA:
• NTT over Z_q, polynomial arithmetic, Keccak-based PRF/PRNG
• PCIe / AXI4 interfacing for hardware-software co-design
• Side-channel awareness: masking, constant-time implementation

PREFERRED:
Publications at CHES, TCHES, IEEE S&P, CCS, or Eurocrypt
Contributions to liboqs, pqclean, or NIST PQC submission code
HLS experience (Vitis HLS / Intel HLS Compiler)
ASIC design flow experience (FPGA-to-silicon roadmap)
Comfortable working across US (SF Bay Area) and EU (Paris) time zones

─── COMPENSATION ───

• Vesting: 4-year / 1-year cliff from partnership date
• Salary: $0 until Seed close
• Post-Seed salary: $150,000–$220,000+ (SF market rate)
• Seed target: $2M–$4M USD
• ESOP pool (10–15%) reserved — NOT deducted from your stake